vioft2nntf2t|tblJournal|Abstract_paper|0xf4ffce7d0d0000007e05020001000600 As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC) implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC) architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. In this paper, the Circuit-Switched (CS) Router was designed and analysed the various parameters such as power, timing and area. The CS router has taken more number of cycles to transfer the data from source to destination. So the pipelining concept was implemented by adding registers in the CS router architecture. The proposed architecture increases the speed of operation and reduces the critical path of the circuit. The router has been implemented using Verilog HDL. The parameters area, power and timing were calculated in 130 nm CMOS technology using Synopsys tool with nominal operating voltage of 1V and packet size is 39 bits. Finally power, area and time of these two routers have been analysed and compared.
U. Saravanakumar1, R. Rangarajan2 and K. Rajasekar3
1,3PSG College of Technology, India,2Indus College of Engineering, India
SoC, NoC, Circuit Switched Router, Worm-Hole Router, Latency
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| Published By :
ICTACT
Published In :
ICTACT Journal on Communication Technology
( Volume: 3 , Issue: 4 , Pages: 646-650 )
Date of Publication :
December 2012
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124
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