vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff97222c000000c1f8000001000c00 This article presents a new design of a single-ended low-power 8 transistor (8T) Static Random-Access Memory (SRAM) bitcell based on Schmitt-Trigger. The proposed cell is designed using a single bitline architecture that eradicates the conflict of design requirements on the access transistors. The proposed cell uses a Schmitt-Trigger based inverter which helps to increase the hold, read and write ability of the bitcell. A selective power gating transistor is also used which increases the write ability and also lowers the power consumption during write operations. Various parameters such as signal to noise margin (SNM), delay, read/write power and leakage power consumption of the proposed bit cell are compared against the conventional 6T SRAM bitcell and other bitcells. The simulations are performed using Cadence Virtuoso Software with a 180nm technology. The proposed bitcell has 1.3x larger area than the conventional bitcell. The results show that the proposed bitcell compares well against all the other considered bitcells and also is a better performer in many parameters.
Sarthak Jain1, R S Gamad2,R C Gurjar3
Shri G.S. Institute of Technology and Science, India1, Shri G.S. Institute of Technology and Science, India2,Shri G.S. Institute of Technology and Science, India3
Static Random-Access Memory (SRAM), Low-Power, Stability, Static Noise Margin (SNM), Schmitt-Trigger
| January | February | March | April | May | June | July | August | September | October | November | December |
| 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 7 , Issue: 3 , Pages: 1178-1188 )
Date of Publication :
October 2021
Page Views :
159
Full Text Views :
1
|