Abstract

The transmission of clock signal is done across the integrated circuit in the presence of buffers and wires in synchronous biomedical systems on-chip architectures. This paper presents the investigation of the driver tree architecture to be used in microprocessor and DSP processors for biomedical image processing applications for clock distribution. In system on chip architecture this design plays an important role. Several clock distribution units like parallel, H-Bridge configurations were implemented in past. A new buffer is designed for the improvement of driving capability in clock distribution. This paper presents the CMOS based clock distribution circuit with better power and drive current. The parameters like power and current are investigated. Predictive technology models for CMOS 90nm technology are used.