Complexity will be the critical issue in VLSI implementation of Image Compression Architectures. Especially it will be predominant issue while dealing with NN based image compression architectures. Due to the development of FPGA, dealing of NN Image Compression Architecture becomes smoother. Furthermore reducing power consumption of those architectures can be deal with CSD algorithms. NN based compression can be added to standard JPEG compression is proved be an efficient strategy for dealing images of high resolution in terms of speed and power. CSD algorithm is proved to provide low power consumption along with low computation time while dealing NN structures. The proposed architecture is hence based on CSD Floating Point Matrix Multiplier (FPMM) and it is synthesized and implemented using Xilinx Vivado Artix7 and Nexys DDR boards. Simulation with MATLAB & Xilinx Vivado is carried out for this work and almost same results are observed.
M Lakshmi Kiran1, K Nikhileswar 2, K Venkata Ramanaiah3
PVKK Institute of Technology, India1, Indian Institute of Technology, Patna, India2, Yogi Vemana University, India3
CSD, FPMM, DDR, FPGA | Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 6 , Issue: 4 )
Date of Publication :
January 2021
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