vioft2nntf2t|tblJournal|Abstract_paper|0xf4ffa4b42b0000002924060001000600 In deep sub-micron memories like DRAM and SRAM, faithful sensing of bit line voltages is becoming very challenging as transistor characteristics mismatch caused by intrinsic variations in manufacturing processes has posed a grave challenge leading to failures of circuits and reductions in yield. This paper addressed these issues and applied a compensation scheme to various schematics of sense amplifiers, which have resulted in a high tolerance to process-induced variations. The schematics, designed with DGFinFET, utilize an enhanced self-compensation technique to surmount disparities in physical transistor characteristics. The recreations of transistor mismatch (threshold voltage, Vt) using the Monte-Carlo technique show that the proposed CCLSA schematic performs correctly even for severe Vt mismatch of 40-50mV. These results are compared with corresponding circuits reported in the literature for the speed, area, and yield. This design also offers up to 20-30% higher yield compared to its uncompensated counterpart and has a reduced penalty for the complexity of circuit and performance. These circuits are easily implementable at 45nm and 32nm technology nodes.
Vivek Harshey1, S K Bansal2
Sant Longowal Institute of Engineering and Technology, India1, Sant Longowal Institute of Engineering and Technology, India2
Compensation, Process Variations, DRAM, FinFET Sense Amplifier, Robustness
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 6 , Issue: 4 , Pages: 1027-1033 )
Date of Publication :
January 2021
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152
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