Abstract

For high speed communication applications; jitter, phase noise and power consumption are most critical parameters required to be considered for PLL designs. A sub harmonically injection locking concept can be used in PLL to reduce jitter and phase noise. Such design is very effective for high frequency applications. This article presents design for low jitter, phase noise, power dissipation for 7.5 GHz Phase locked loop using sub harmonic injection technique with auto adjusted Delay locked loop in 180-nm CMOS technology. The measured phase noise at 1 MHz reference offset frequency is 122.31 dBc/Hz with rms jitter is 127 fs. The overall power dissipation is 13.99 mW for proposed design.