vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff9a562b000000d844040001000200 An area efficient, fixed width multiplier using booth encoding is done in this work. The work is further extended to accommodate the error correction feature. As in many signal processing products fast and efficient processing elements are required, the demand increases day by day. This work is one such finding to meet the standard of today’s contemporary technology. The proposed methodology suits well for the discrete cosine transform application. A new multiplier architecture using booth encoding is done. The architecture includes a tree based carry save reduction unit with parallel prefix adder and the compensation circuit. The work is carried out in 180nm technology using predictive technology models. The circuits are implemented using SPICE models and the results are obtained. For equal probability the inputs of different blocks are kept ‘1’ or ‘0’ in equal numbers. The frequency of operation is 100MHz. The proposed design will be compared with the existing methods. The robustness will be checked using skewed distribution. The project will be further extended to design for high speed and advanced technology of 90nm in future.
S Ravindrakumar1, V M SenthilKumar2, S Jayasri3 D Nithya4 Jyotsna Siva5
Sri Shakthi Institute of Engineering and Technology, India1, Malla Reddy College of Engineering and Technology, India2, IRRD Automatons, India3,4,5
Multiplier, Carry Save Reduction, Booth Multiplier, Error Compensation
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 5 , Issue: 3 , Pages: 820-824 )
Date of Publication :
Januray 2019
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