vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff2e97280000006531020001000000
Leakage current has been a vital issue in system on-chip systems with the contemporary sub-micron advancements. It has consequently turned out to be vital to control the current and address the issue from the architectural level. This paper presents different models of Static Random Access Memory (SRAM) cells to diminish the leakage current. The types of leakage current considered in this paper are gate leakage and sub threshold leakage. Two traditional leakage reduction methods have been connected to 6T SRAM cell with memristor and results have been analysed. This is a non-volatile memory since it utilizes memristor. Non-volatile 6T SRAM cell with stack and sleep transistor indicates a significant decline in leakage current when compared with basic 6T SRAM cell. All the proposed work has been completed by utilizing Cadence Virtuoso at 180nm technology.