vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff2a9728000000d479010001000100 This paper presents the design and verification of folded cascode operational amplifier using conventional CMOS technology. The design specification has been decided and accordingly the aspect ratios are designed with the help of design equations. Design have been carried out on Mentor Graphics EDA tool using TSMC 180nm and 130nm, 32nm on HSPICE EDA tool using CMOS technology. Pyxis schematic and ELDO version 11.2 simulation tool is used for designing and Pyxis layout and Calibre tool for verification of the layout. For 180nm technology the pre-layout results are calculated and same are implemented in the EDA tool and gives output values as gain 67.6dB, Phase margin 63º, & Unity Gain Bandwidth 256MHz. The output swings up to 1.7266V with power dissipation of 649.7735µW. The post-layout simulations i.e. physical verification is done and verified using DRC checker, LVS report and PEX results. The performance parameters of folded cascode opamp are compared using 180nm, 130nm, and 32nm CMOS technology where the results show reduction in values but significant fall in power dissipation is observed which is an advantage. Other performance parameters can be improved by using FinFET, CNFET which can be an alternative for CMOS at deep sub-micron levels.
Saurabh Waykole1, Varsha S Bendre2, A K Kureshi3
Pimpri Chinchwad College of Engineering, India1,2, Vishwabharati Academy’s College of Engineering, India3
Moore Law, TSMC 180nm, 130nm, 32nm, Mentor Graphics, HSPICE, Physical Verification, DRC, LVS, PEX
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 4 , Issue: 3 , Pages: 619-624 )
Date of Publication :
October 2018
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