vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff149d270000008b15000001001500
In network security Image Steganography is one of the crucial data hiding technique. In this paper a new architecture was proposed for with and without pipelining technique for LSB Matching Revisited steganography algorithm and it is implemented in FPGA using Verilog HDL. The design motto is to increasing the speed, reducing the clock cycle by performing embedded and fetching operation parallel, reduces the complexity in both transmitting and receiving side and also we can send more confidential message due to the large cover image (128×128×8) size which we have used here. In the transmitting side data hiding is performed and receiving side extraction is performed. Whole entire process is takes place in both hardware and software, finally, result was analysed for both software and hardware level. From the outcome investigation, Pipelined model will give a superior outcome while contrasting with non-pipelining mode as far as less inserting time contrasted with the non-pipelined mode.