vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff73a9250000006d3b020001000200 This work presents an elegant methodology using pulsed latch instead of flip-flop without altering the existing design style. Pulsed-latch technique retain the advantages of both latches and flip-flops and thus one can achieve both high speed and lower power consumption simultaneously. In this work, pulsed latch technique has been used to reduce the delay of various shift registers without increasing any power consumption. In very high speed VLSI circuits due to heavy pipelining there is requirement of low power edge triggered flip-flops. However, for low power consumption in these very high speed VLSI circuits, the migration from flip-flop to pulsed latch technique has become a great success. In the proposed work, non-overlapped delayed pulse clock has been used in pulse latch technique to eliminate the timing problem between the pulsed latches. All the proposed shift registers have been designed in 90 nm CMOS technology and their functionality have been verified using Cadence Virtuoso. From this work, it has been concluded that, the pulse latch technique reduces the power consumption significantly in the designed registers and overall there is an improvement in power delay product. Further, it is pertinent to mention that the proposed registers require less number of transistors for their implementation as compared to conventional versions.
Vandana Niranjan
Indira Gandhi Delhi Technical University for Women, India
Low Power, Non-Overlapped Pulse, Pulsed Latch Technique, Flip-Flop, Delay, Shift Register
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 3 , Issue: 4 , Pages: 494-502 )
Date of Publication :
January 2018
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