Home >>Journals >>ICTACT Journal on Microelectronics ( Volume: 3 , Issue: 2 )
A 16-BIT HIGH-SPEED MULTIPLIER DESIGN BASED ON KARATSUBA ALGORITHM AND URDHVA-TIRYAGBHYAM THEOREM USING MODIFIED GDI CELLS FOR LOW POWER AND AREA CONSTRAINTS
Abstract
vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff0d32240000004718010001000700
The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva- Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.

Authors
Bobby Nelson, Ravi Tiwari
Shri Shankaracharya Technical Campus, India

Keywords
Area-Efficient, GDI, Karatsuba Algorithm, Multiplier, Urdhva- Tiryagbhyam Theorem
Yearly Full Views
JanuaryFebruaryMarchAprilMayJuneJulyAugustSeptemberOctoberNovemberDecember
000000000000
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 3 , Issue: 2 , Pages: 398-403 )
Date of Publication :
July 2017
Page Views :
90
Full Text Views :

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.