A 16-BIT HIGH-SPEED MULTIPLIER DESIGN BASED ON KARATSUBA ALGORITHM AND URDHVA-TIRYAGBHYAM THEOREM USING MODIFIED GDI CELLS FOR LOW POWER AND AREA CONSTRAINTS

Abstract
The paper entails the design of a 16-bit multiplier with the combined application of Karatsuba algorithm and the Urdhva- Tiryagbhyam (UT) theorem and the implementation of the multiplier architecture in Modified-Gate-Diffusion-Input (Mod-GDI) cells for improving the area and power constraints in the proposed novel hybrid multiplier.

Authors
Bobby Nelson, Ravi Tiwari
Shri Shankaracharya Technical Campus, India

Keywords
Area-Efficient, GDI, Karatsuba Algorithm, Multiplier, Urdhva- Tiryagbhyam Theorem
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 3 , Issue: 2 )
Date of Publication :
July 2017

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