vioft2nntf2t|tblJournal|Abstract_paper|0xf4ffd37623000000aed3050001000800 Multiplier is a crucial block of most of the digital arithmetic applications. With the advancement in the field of VLSI, achieving high speed and low power consumption has become a major concern for the designers. As multiplier block consumes large amount of power and has a major role to play in the speed of the circuit therefore its optimization will improve the performance of the circuit. The process of multiplication is implemented in hardware using shift and add operation, so use of efficient adder circuit will lead to improved multiplier. In this paper, reduced complexity Wallace tree multiplier circuit is proposed that uses efficient and improved adder. The circuits are designed using 90nm technology and simulated in Cadence Virtuoso. The proposed Wallace tree structure offers a decrement of approximately 70% in dissipation of power, approximately 86% in power delay product and 60% in area. The proposed multiplier is suitable to use in applications such as DSP structures, ALU’s and several low power and high speed arithmetic applications.
Meenali Janveja1, Vandana Niranjan2
G. L Bajaj Institute of Technology and Management, India1, Indira Gandhi Delhi Technical University for Women, India2
Wallace Tree, Full Adder, Pass Transistor Logic, Power Dissipation, Delay
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 3 , Issue: 1 , Pages: 370-374 )
Date of Publication :
April 2017
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132
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