Home >>Journals >>ICTACT Journal on Microelectronics ( Volume: 2 , Issue: 3 )
AREA EFFICIENT, LOW QUIESCENT CURRENT AND LOW DROPOUT VOLTAGE REGULATOR USING 180nm CMOS TECHNOLOGY
Abstract
vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff8b82210000000056050001000a00
This paper illustrates the design and implementation of a Low Drop out voltage regulator which consumes low power and occupies less area. The regulator uses single stage error amplifier hence area consuming compensation capacitor is avoided. It needs only 16 µA quiescent current making it suitable for low power applications. The proposed regulator has been designed in 180 nm CMOS technology and performance is tested using spice tool and layout is done using MAGIC VLSI tool. Simulation results show that the LDO has a line regulation of 0.001V/V and load regulation of 0.002V/mA. The LDO occupies an area of 70µm ? 80µm and power dissipation is 20µW.

Authors
Guruprasad, Kumara Shama
Manipal University, India

Keywords
Linear Regulator, Low Drop-Out, Low Power, Power Management
Yearly Full Views
JanuaryFebruaryMarchAprilMayJuneJulyAugustSeptemberOctoberNovemberDecember
000000000000
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 2 , Issue: 3 , Pages: 288-292 )
Date of Publication :
October 2016
Page Views :
167
Full Text Views :

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.