ANALYSIS OF STATIC NOISE MARGIN FOR NOVEL POWER GATED SRAM

Abstract
Data stability is one of the important parameter of SRAM with scaling of CMOS technology. However the move to nanometer technology not only nodes has increased, but the variability in device characteristics has also increased due to large process variations. Static random access memory (SRAM) is a popular component which is used in modern microprocessors and occupies a considerable chip area. It is useful to store the data as well as read and write operation. The performance of SRAM circuit is measured with data stability and read-write SNM (Static Noise Margin). A novel power gated SRAM cell is presented in this paper with enhanced data stability and reduced leakage power. The data becomes completely isolated form bit line during read operation in new power gated SRAM. The SNM of the new power gated cell is thereby increased by 2 times in comparison to a conventional six transistor (6T) SRAM cell. The paper also covers the comparative analysis and simulation of both SRAM cell on the basis of Read Noise Margin and Write Noise Margin. The novel power gated SRAM cell has larger read and write SNM as compared to conventional 6T SRAM cell at different technologies. All results are carried out on 45nm, 32nm and 22nm CMOS technology using HSPICE simulation tool.

Authors
Balotia Suresh Kumar, Amit Mahesh Joshi
Malaviya National Institute of Technology, India

Keywords
Cell Ratio, Power Gated, Read Margin, Static Noise Margin, Write Margin
Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 2 , Issue: 3 )
Date of Publication :
October 2016

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