vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff455c1d000000312f010001000700 In this paper a study of power efficient pulse triggered flip flops was conducted by adopting a pulse control scheme (PCS), named conditional pulse enhancement. The conditional pulse enhancement scheme consists of a simple pass transistor ‘AND’ gate design and a pull up ‘pMOS’. This set up reduces circuit complexity and removes the pulse generation control logic from the critical path, which facilitate a faster discharge operation as well as improvise the discharge speed conditionally. In this project, the effect of conditional pulse enhancement scheme on the power as well as performance of conventional flip flop such as ep-DCO, ep-CDFF, ip-DCO, are analyzed. The performance analysis was carried out by adopting 180nm CMOS technology. The simulation results reveal that implicit flip flops with conditional pulse enhancement scheme outperforms the conventional flip flops in terms of power and timing characteristics
Thara Sebastian, A. Aravindhan
Saintgits College of Engineering, India
Pulse Triggered Flip Flop (P-FF), Pulse Control Scheme (PCS), Pulse Enhancement, Pass Transistor AND, Pulse Generation
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 1 , Issue: 3 , Pages: 120-123 )
Date of Publication :
October 2015
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