FPGA BASED ASYNCHRONOUS PIPELINED MB-OFDM UWB
TRANSMITTER BACKEND MODULES

Abstract
In this paper, a novel scheme is proposed which comprises the advantages of asynchronous pipelining techniques and the advantages of FPGAs for implementing a 200Mbps MB-OFDM UWB transmitter digital backend modules. In asynchronous pipelined system, registers are used as in synchronous system. But they are controlled by handshaking signals. Since FPGAs are rich in registers, design and implementation of asynchronous pipelined MBOFDM UWB transmitter on FPGA using four-phase bundled-data protocol is considered in this paper. Novel ideas have also been proposed for designing asynchronous OFDM using Modified Radix-24 SDF and asynchronous interleaver using two RAM banks. Implementation has been performed on ALTERA STRATIX II EP2S60F1020C4 FPGA and it is operating at a speed of 350MHz. It is assured that the proposed MB-OFDM UWB system can be made to work on STRATIX III device with the operating frequency of 528MHz in compliance to the ECMA-368 standard. The proposed scheme is also applicable for FPGA from other vendors and ASIC.

Authors
M. Santhi, G. Lakshminarayanan
National Institute of Technology, Tiruchirappalli, Tamil Nadu, India

Keywords
Mobile Ad hoc network, Energy efficient routing, Energy balance, Transmission power control, Energy dissipation rate.
Published By :
ICTACT
Published In :
ICTACT Journal on Communication Technology
( Volume: 1 , Issue: 1 )
Date of Publication :
March 2010

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