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EFFICIENT LOW-POWER CMOS VLSI DESIGN: LEVERAGING FEDERATED LEARNING FOR ADIABATIC SWITCHING

Abstract Low-power CMOS VLSI circuits are crucial for energy-efficient digital systems, particularly in time-domain mixed-signal (TD-MS) applications. Despite advancements, traditional digital circuits often fall short in energy and area efficiency. Conventional digital circuits struggle with high energy consumption and area utilization, especially in data acquisition, conversion, key generation, and protection tasks. There is a need for more efficient alternatives. This study presents a novel TD-MS circuit design incorporating artificial neural networks (ANN) and reversible perturbation adiabatic switching. We compared these TD-MS circuits against a baseline digital implementation in 65nm technology. Full-stack SPICE simulations were used for both setups. The TD-MS circuits shown a 670× energy/frame savings compared to the embedded digital system. Area efficiency improved by 3×, and energy savings were 3.2× compared to the digital baseline. Authors S. Jayashree1, K. Malarvizhi2, S. Karthik3 SNS College of Engineering, India1,3, Kumaraguru College of Technology, India2 Keywords Low-power CMOS, Time-Domain Mixed-Signal, Energy Efficiency, SPICE Simulations, Neural Networks Yearly Full Views January February March April May June July August September October November December 0 0 0 0 0 0 0 14 0 0 0 0

Published By : ICTACT Published In : ICTACT Journal on Microelectronics ( Volume: 10 , Issue: 2 , Pages: 1822 - 1829 ) Date of Publication : July 2024 DOI : 10.21917/ijme.2024.0315 Page Views : 47 Full Text Views : 14