The proliferation of IoT edge devices demands energy-efficient VLSI circuits to prolong battery life and enhance device autonomy. This study addresses the design and optimization of low-power VLSI circuits tailored for IoT edge devices. In the background, the escalating need for energy-efficient solutions in IoT edge devices is outlined, emphasizing the significance of optimizing VLSI circuits for low power consumption. Methodology-wise, a comprehensive approach integrating architectural, circuit-level, and algorithmic optimizations is proposed to achieve optimal power efficiency while meeting performance constraints. The contribution of this research lies in the development of novel techniques for minimizing power consumption in VLSI circuits, including dynamic voltage scaling, clock gating, and subthreshold operation. Results demonstrate significant reductions in power consumption while maintaining adequate performance levels, thereby extending the operational lifespan of IoT edge devices. Findings underscore the effectiveness of the proposed methodologies in enhancing energy efficiency without compromising functionality. This research paves the way for the widespread deployment of low-power VLSI circuits in IoT edge devices, facilitating their seamless integration into energy-constrained environments.
S. Bhaggiaraj1, S. Maria Antony2, Bulasala Uma Sankar3
Sri Ramakrishna Engineering College, India1, KIT-Kalaignarkarunanidhi Institute of Technology, India2, V.R.S & Y.R.N College of Engineering and Technology, India3
IoT, Edge Devices, Low-power VLSI Circuits, Optimization, Energy Efficiency
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 10 , Issue: 1 , Pages: 1727 - 1731 )
Date of Publication :
April 2024
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