This research explores the design of Evolutionary Quantum Computing (EQC) tailored for ultra-compact nano-electronic circuits within Very-Large-Scale Integration (VLSI) technology. The conventional digital circuits face limitations in terms of miniaturization, power consumption, and processing speed, prompting the need for innovative paradigms. The research identifies a critical gap in the existing literature, as there is a scarcity of studies focusing on the synergistic integration of evolutionary algorithms with quantum computing in the context of VLSI. The proposed methodology involves the development of a novel hybrid quantum-classical architecture, leveraging evolutionary algorithms to optimize quantum gates placement and connectivity within nano-electronic circuits. This approach is anticipated to address the challenges associated with quantum gate layout and improve the overall efficiency of quantum computations. The simulations are conducted to validate the proposed EQC design, and the results are expected to demonstrate superior performance metrics in terms of circuit density, power consumption, and computational speed.
N.K. Anushkannan1, P. Umamaheswari2, Rakesh Kumar3, T. Lakshmi Narayana4
Kathir College of Engineering, India1, SRM Institute of Science and Technology, India2, University College of Engineering and Technology, Bikaner, India3, KLM College of Engineering for Women, India4
Evolutionary Quantum Computing, Nano-Electronic Circuits, VLSI, Quantum-Classical Hybrid Architecture, Quantum Gate Optimization
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 9 , Issue: 4 , Pages: 1687 - 1692 )
Date of Publication :
January 2024
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