vioft2nntf2t|tblJournal|Abstract_paper|0xf4fffe13310000004bb2100001000100 Finite Impulse Response (FIR) filters are widely used in various fields of engineering like image processing, signal processing, communication, consumer electronics etc. Power, area, and delay are primary performance parameters and design of optimized FIR filters meeting these requirements is desired in all fields of application. Simulated annealing algorithm is used for solving discrete optimization problems. In this paper, discrete FIR filters are designed using simulated annealing for FPGA and ASIC implementation. The proposed FIR filters are designed using 2-input logic gates and universal logic module 2:1 multiplexer. The proposed FIR filters designed using simulated annealing are compared with FIR filters designed using Wallace tree multipliers and Dadda multipliers. Experiments reveal that proposed FIR filter with logic gates are suitable for both FPGA and ASIC implementations and MUX based FIR filters are promising for FPGA implementation. It is observed that proposed FIR filters saved maximum of 11.11% of area and 33.45% of power over conventional designs.
Y.J. Pavitra1, S. Jamuna2, J. Manikandan3
PES University, India1,3, Dayananda Sagar College of Engineering, India2
Discrete FIR Filter, Simulated Annealing, Optimization, Performance
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 8 , Issue: 4 , Pages: 1442 - 1446 )
Date of Publication :
January 2023
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