vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff23b42e000000ab4a100001000700
Authors implement area efficient high speed dual edge triggered flip flop circuit with low power technique. PTL and CMOS technique are introduced with 45nm, 90nm technology on cadence virtuoso 16.1 gpdk model library. A comparative study of average power and delay at room temperature at .5V, .8V and 1Vhas been done. Pass transistor logic enhancing switching activity and dynamic signal driving schemes help in power consumption. By reducing number of transistor, components and clock loads performance of proposed circuit has been improved.