vioft2nntf2t|tblJournal|Abstract_paper|0xf4ff22b42e000000ab4a100001000500 This paper presents a study to understand the behaviour of latest dualedge triggered flip flops (DETFFs) under extensive variations in voltage, temperature, frequency, data activity and corner cases for power, area and speed of operations. Six state-of-art DETFFs were considered and compared in 32 nm CMOS technology for their robustness under “Process, Voltage and Temperature (PVT)” variations. Simulations were carried out on T-SPICE with nominal operating conditions of 200 MHz clock frequency, 25 °C temperature, 0.9 V voltage and at 50% data activity. Results obtained showed that Khan’s FF saves minimum of 13.82% power to maximum of 44.86% at nominal conditions. The Khan’s FF is the fastest among all with minimum of 46.47% advantage over the others. At higher temperatures (>75 ° C), Lee’s FF outperforms all other designs. Wang’s FF is the most area efficient FF and requires minimum of 2.03% to maximum of 24.92% less area. The DETFFs were tested for power efficiency as a 4-bit shift register, Lee’s FF dissipated least power followed by Khan’s FF.
Owais Ahmad Shah1,Geeta Nijhawan2,Imran Ahmed Khan3
Manav Rachna International Institute of Research and Studies, India1,2,Jamia Millia Islamia, India3
Flip Flop, CMOS Digital Circuit, Low Power, Dual-Edge Triggered, Shift Register
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| Published By :
ICTACT
Published In :
ICTACT Journal on Microelectronics
( Volume: 8 , Issue: 3 , Pages: 1400 - 1407 )
Date of Publication :
October 2022
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